It is generally recognized that some semiconductor devices are susceptible to damage from electrical overstress conditions (EOS). These conditions occur when the voltage or amperage ratings for a circuit are exceeded. Exemplary electrical overstress conditions include electrostatic discharge (ESD), transient conditions, latch-up, incorrect polarity connections, etc. The electrical overstress conditions are typically characterized by over-voltage and over-current stress events.
Providing protection from overstress conditions continues to increase in importance as the sensitivity of semiconductor devices also increases. An increasing number of semiconductor devices are sufficiently sensitive that a flow of charge imparted to a device during an overstress condition results in permanent damage to the semiconductor device.
Accordingly, it is highly desired to protect semiconductor devices from electrostatic discharge events and other electrical overstress conditions. Some solutions have attempted to minimize the accumulation of electrostatic charge to prevent electrostatic discharge. Other approaches implement electrostatic discharge components within the electrical or semiconductor components themselves to shunt stress currents and protect sensitive circuitry.
Such methods of providing electrostatic discharge components are typically successful at alleviating susceptibility to electrostatic discharge damage. However, the implementation of stress protection components can introduce other drawbacks. For example, the electrostatic discharge protection devices can increase capacitance at the I/O pads resulting in decreased performance of the semiconductor device. Decreased performance is highly undesirable inasmuch as speed of some semiconductor devices is of paramount importance. Another exemplary drawback includes the consumption of additional surface area of the substrate to implement the electrical overstress and electrostatic discharge protection circuitry.
Referring to FIG. 1, a conventional input/output (I/O) pad cell configuration of an integrated circuit device is generally depicted as reference number 10. The depicted I/O pad cell 10 is configured to couple with external circuitry via a pad 12 and with internal circuitry of the device via a buffer 14. An ESD component 16 is coupled with pad 12 in the depicted conventional arrangement of I/O pad cell 10. The illustrated ESD protection technique provides robust ESD protection inside the individual I/O pad cell 10. This conventional arrangement enables individual I/O pad cells 10 to have stand-alone ESD protection and allows flexibility in product design. ESD component 16 comprises a PMOS device 17 coupled with an NMOS device 18 in the depicted arrangement.
The illustrated I/O pad cell 10 also includes an output driver 19, resistor 20 and voltage clamp configuration 21 intermediate pad 12 and buffer 14. Control circuitry internal to core circuitry of the integrated circuit device (not shown) is coupled via a connection 22 with output drivers 19 for controlling the operation thereof.
While the arrangement depicted in FIG. 1 may provide adequate ESD protection, associated drawbacks exist with such a configuration. In particular, the illustrated configuration does not provide optimized use of chip area for implementing ESD protection. For example, ESD component 16 includes NMOS device 18 intermediate I/O pad 12 and the V.sub.ss bus which is typically large in size to provide ESD protection. The size of I/O pad cell 10 is dictated by the total ESD protection width of ESD component 16. Continued I/O scaling will demand further reduction in the total chip area used for ESD protection. In addition, provision of additional ESD protection circuitry (e.g., ESD component 16) reduces performance characteristics of the integrated circuitry device.
Therefore, a need exists for improved devices and methodologies which provide protection from electrical overstress conditions and overcome the drawbacks associated with the prior art.